The present invention relates generally to memory devices. More particularly, the present invention relates to a flash memory device having a dual bank, simultaneous operation architecture.
Flash memory devices are increasingly popular for providing data storage in data processing systems. Flash memories are non-volatile, meaning that stored data is retained when power is interrupted to the memory. Flash memories provide read and write capability. Data that has been written in a flash memory may be erased on a sector-by-sector basis and erased sectors may be subsequently rewritten. Flash memories provide large capacity, with current generations storing 32 MB or more of data. Also, flash memories provide fast access, with read access times on the order of 125 ns or less.
Next generation memories are being designed which extend the features and capabilities of conventional flash memories. Conventional flash memories have a limitation in that a write operation and a read operation are mutually exclusive. Write and read operations are conventionally embedded operations requiring a sequence of steps including on-chip voltage generation and logical operations. The embedded read and write operations are under control of a state machine. The write operation consists of erase, program and verify operations which are relatively slow, taking on the order of microseconds to execute. During the erase, program and verify operations, read operations are precluded. This can be inconvenient for the user.
Accordingly, one extension of conventional memory design is dual bank, simultaneous operation architecture. Such an architected memory has an array of core cells that is separated into two independent banks referred to as the upper bank and the lower bank. The circuitry necessary for reading and writing data in each bank is independent for each bank. In this manner, a read operation can occur in one bank while a write operation occurs in another bank. Control circuitry in the form of an on-chip state machine controls the internal processes needed to read and write the data in the separate banks.
Another limitation of conventional flash memories is a relatively slow asynchronous read access time. This corresponds to the delay from the application of a valid address to the address pins of the memory to the presentation of valid data at the output pins of the memory. As noted, in current generation memories, the asynchronous access time is on the order of 125 ns. However, many current data processing systems require data access times much less than this.
Accordingly, burst read capability has been developed. In burst read mode, a clock signal is provided to the memory and a sequence of contiguous data is read from the memory on each cycle of the clock, which can be, for example, 25 ns. Externally, the burst read data all have sequential addresses. Internally, the burst read data are stored in core cells having a common row or word line. Once the common word line is selected, all data bits stored in core cells on that word line can be read out, again under control of the on-chip state machine. This substantially reduces the read access time for entire burst, although the asynchronous access time must elapse before the first burst data is available. This is particularly efficient, for example, for accessing boot code by a data processing system on power up or after a reset, when a sequence of consecutive instructions and data are required for booting the system.
For next generation devices, it will be desirable to combine simultaneous operation with burst read operation. However, when embedded processes are performed under control of the state machine, other commands are ignored or locked out. Conventional flash devices do not allow the user to issue any other command once an embedded erase or program command has been given. This ensures that the embedded algorithm will not be disturbed. Accordingly, there is a need for a method and apparatus for simultaneous execution of command modes in a flash memory.